Electrical and Computer Engineering
University of California, San Diego
San Diego, CA 92092-0100

Phone: (858) 281-9076
Email: umallapp@ucsd.edu

Research Interests (AI for Design Optimization and Efficient ASIC Design for AI Algorithms)

Machine Learning to improve chip-design convergence, Physical Design fundamental algorithms and optimization techniques.
Today, an Integrated Chip design (encompassing logic synthesis, placement, routing and optimization) involves optimization/analysis over billions of variables (physical and electrical components) interweaved with complex objective functions (wirelength, power, performance and area). The Electronic Design Automation (EDA) industry offers many state-of-the-art optimization and analysis tools that help in reaching our goal to design and manufacture a chip. All of these tools (developed for over 30 years) suffer from their inability to learn from their past behavior. Therefore, any small change in the problem needs a completely new start. Also, to reduce the space of solutions (usually exponential), multiple heuristics and meta-heuristics are used; with the eventual goal being, faster convergence of the algorithm. These choices of heuristics could result in sub-optimal solutions. Exploration-explotation entwined with learning optimal sequences of decisions is the key paridigm of reinforcement learning. With the latest GPUs offering 1000s of logic cores, exploring large datasets and training over larger datasets is not a bottleneck anymore. Formulating complex optimization problems as learning problems can leverage the computation captablity, that these GPU cores offer. Since majority of the problems in chip-design-cycle can be formulated as optimization over directed acyclic graphs, my research is projected towards using a combination of graph embeddings (using neural networks) and reinforcement learning. Major portion of research during my Ph.D is towards this pursuit. To complete the cycle, I started working on designing efficient ML accelerators. This involves formulating hardware-friendly inference algorithms, software-friendly architectural explorations, low-level design in verilog, physical layout design (Placement & Routing, Power Delivery Network Synthesis, Timing and Power analysis) and eventual realizatin of the physical chip by chip-tapeout process (40nm). For me, this work started as a learning curiosity in the pursuit of connecting various skills that I have attained over the last decade, and eventually helped me to realize the purpose of their collective impact as compared to their individual contributions.

Biographical Sketch

I received my Dual Degree (Bachelor of Engineering in Electrical and Electronics Engg & Masters in Physics) from BITS-Pilani in 2011. I am currently a third year Computer Engineering Ph.D. student at University of California San Diego, advised by Prof. C. K. Cheng (Distinguished Professor at the Department of Computer Science and Engineering and an Adjunct Professor at the Department of Electrical and Computer Engineering, UCSD). Before joining UCSD for his Ph.D., I worked as a chip design engineer in India for over six years.